Exact timestamps when a signal transitions from low-to-high or high-to-low (e.g., Drive High at 2ns).
Manages compressed air, vacuum, and cooling fluid loops. Pin Electronics (PE) & Resources
When the tester isn't behaving, engineers typically follow these steps:
Let’s walk through real-world tasks and which manual sections to reference. verigy 93k tester manual
Using C++ and specialized test methods. Debugging: Utilizing the debugger to analyze failure data.
The Verigy 93000 utilizes a highly scalable, "tester-per-pin" architecture. This means every individual pin on the tester operates independently with its own dedicated resources, maximizing flexibility and minimizing test times. Key Hardware Components
Uses an eclipse-based Integrated Development Environment (IDE) with a centralized database instead of disconnected text files. 3. Core Component Files & Configurations Exact timestamps when a signal transitions from low-to-high
Signals like START_TEST , END_TEST , and BIN_RESULTS are transmitted between the tester and the handler using hardware interfaces (TTL/GPIB) or network-based soft-protocols (like Advantest's standard driver interfaces). Multi-Site (Parallel) Testing Optimization
Number and Mix of Digital, Mixed Signal, DPS, RF. June 2014 All Rights Reserved - ADVANTEST CORPORATION Hardware Overview Unit 2 - AT93000 System User Manual - Multilane
Functional testing verifies the logic of the DUT by feeding structural pattern data through the pin channels. Using C++ and specialized test methods
Efficiently managing large pattern files is a recurring theme in the manual. It provides instructions on converting third-party formats (like WGL or STIL) into the native 93k binary format. Key Calibration and Maintenance Procedures
While the hardware documentation outlines what the machine can do, the software documentation outlines how to do it. The V93000 operates primarily on the SmarTest software environment. The manuals covering SmarTest are often the source of the steepest learning curve for new engineers.
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